This invention relates generally to automatic test equipment for programmable logic devices, and in particular to methods and circuits for precisely placing signal transitions on the input pins of programmable logic devices.
Most semiconductor devices are tested at least once using some form of automated test equipment (generally, a xe2x80x9ctesterxe2x80x9d). Testers generally have a xe2x80x9cper-pinxe2x80x9d architecture in which separate xe2x80x9cchannelsxe2x80x9d within the tester generate or measure one signal corresponding to a single input or output pin on a device under test (DUT). Each channel is separately controlled to generate or measure a different signal. A pattern generator, the function of which is to send commands to each channel to generate or measure one test signal for each of many test periods, controls the various channels. Each channel generally contains at least one edge generator programmed to generate a signal transition, or xe2x80x9cedge,xe2x80x9d at a certain time relative to the start of each test period.
Testers must place accurately timed edges at the various pins of a device under test to make accurate pin-to-pin measurements. When properly calibrated, testers with hundreds or even thousands of channels are only able to reduce the relative error between channels to somewhere in the range of xc2x1500 ps to xc2x11 ns. All measurements require at least two edges be placed, so the cumulative measurement error inherent in the tester can contribute somewhere between 1 ns and 2 ns of uncertainty. Unfortunately, this inherent tester error often exceeds the value of the parameter being measured. To make matters worse, the test boards used to connect the tester channels to device pins can contribute different delays for different channels, adding to the timing uncertainty. There is therefore a need for a means of more precisely placing edges on the pins of devices under test.
A number of engineers employed by Xilinx, Inc., the assignee of the present application, addressed the need for a more precise means of placing edges. The resulting invention is described in U.S. patent application Ser. No. 09/737,996 entitled xe2x80x9cCircuit For Measuring Signal Delays of Synchronous Memory Elements,xe2x80x9d by Siuki Chan and Christopher H. Kingsley, which is incorporated herein by reference. A relevant portion of that application is reproduced below in connection with FIGS. 1-3.
FIG. 1 depicts a conventional tester 100 connected to a device under test (DUT) 110. In the example, DUT 110 is a field programmable gate array (FPGA). DUT 110 includes a coincidence detector 120 that can be used to calibrate tester 100 to produce coincident edges on device input pins 125A and 125B, two of the many pins 125 on DUT 110.
Coincidence detector 120 connects to three input paths A, B, and R and an output path OUT. These four paths connect to respective tester leads 130A, 130B, 130R, and 130Q through respective device pins. Coincidence detector 120 includes an XOR gate 135 and a flip-flop 140. Tester 100 initializes coincidence detector 120 by presenting a positive pulse on lead 130R, thus resetting flip-flop 140.
In one embodiment, DUT 110 is a Virtex(trademark) FPGA available from Xilinx, Inc., of San Jose, Calif. Virtex(trademark) FPGAs include configurable logic blocks that can be configured to instantiate coincidence detector 120. For more information about Virtex(trademark) and other types of FPGAs for use with the invention, see, for example, pages 3xe2x80x943 thru 3-22 and 4-3 thru 4-69 of xe2x80x9cThe Programmable Logic Data Book,xe2x80x9d (1999) from Xilinx, Inc., incorporated herein by reference.
FIG. 2A is a waveform diagram 200 illustrating the case in which simultaneous edges of the same polarity are presented on each of pins 125A and 125B. As is conventional, XOR gate 135 outputs a logic one if the signals on input paths A and B have opposite logic levels (i.e., A=1 and B=0 or A=0 and B=1). Because each of the signals on paths A and B transition at the same instant in FIG. 2A, the logic levels on paths A and B are always the same. The output of XOR gate 135 therefore remains a logic zero. Output path OUT also remains at logic zero in the absence of a positive-going edge to clock the flip-flop.
FIG. 2B is a waveform diagram 210 illustrating an edge (i.e., signal transition) 215 on path A arriving before an edge 220 on path B. XOR gate 135 will output a logic one during the time separating edges 215 and 220 when the signals on paths A and B are at opposite logic levels. The positive-going edge 225 on the output of XOR gate 135 will clock flip-flop 140, causing flip-flop 140 to store the logic one on data terminal D and to output the stored level on output path OUT. The logic one on output path OUT indicates that edges 215 and 220 are not coincident.
FIG. 2C is a waveform diagram 230 illustrating an edge 235 on path A arriving before an edge 240 on path B. The edges are closer than in FIG. 2B, so XOR gate 135 outputs a logic one for a shorter period. The short pulse is still sufficient to clock flip-flop 140, so flip-flop 140 outputs a logic one, indicating that edges 235 and 240 are not coincident.
FIG. 2D is a waveform diagram 250 illustrating an edge 255 on path A arriving only slightly before an edge 260 on path B. The signal transitions are spaced far enough apart so that XOR gate 135 exhibits a small voltage spike 265. However, the small spike is insufficient to clock flip-flop 140, and therefore does not affect a change on line OUT. Thus, coincidence detector 120 will indicate coincident signals although edges 255 and 260 are not exactly coincident. The maximum delay between edges for which coincidence detector 120 indicates coincidence determines the resolution of coincidence detector 120, and may vary considerably depending upon the selected type of coincidence detector.
FIG. 3 is a flowchart 300 illustrating a method for estimating the skew between pins 125A and 125B of FIG. 1. First coincidence detector 120 is instantiated on DUT 110 (step 305). In an embodiment in which DUT 110 is an FPGA, coincidence detector 120 can be created from configurable logic using conventional FPGA programming techniques.
Tester 100 places edges on each of pins 125A and 125B (step 310). These edges are spaced sufficiently in time to ensure coincidence detector 120 indicates the signals are not coincident. In the example of FIG. 3, the edge on pin 125A leads the edge on pin 125B. Then, using the following sequence of steps, the spacing between the two edges is reduced incrementally until coincidence detector 120 indicates the edges are coincident.
Assuming the edges are sufficiently spaced for coincidence detector 120 to output a logic one (decision 315), the channel in tester 100 corresponding to pin 125A is adjusted to move the leading edge on pin 125A toward the trailing edge on pin 125B (step 320). Adjusting the delay associated with a given channel is well within the skill of those familiar with operating testers. Coincidence detector 120 is then reset and the process returns to step 310 in which the new pair of edges, now more closely spaced, are presented on pins 125A and 125B.
By cycling through steps 310, 315, and 320, the delay separating the edges on pins 125A and 125B is incrementally reduced until coincidence detector 120 indicates that the two edges are coincident (in decision 315). The relative timing of the two edges (i.e., the first skew data) is then recorded (step 325), in memory within tester 100, for example.
Next, tester 100 again places edges on each of pins 125A and 125B (step 330). This time, however, the edge on pin 125A is set to trail the edge on pin 125B by an amount sufficient to ensure that coincidence detector 120 indicates that the signals are not coincident. Then, using the following sequence of steps, the spacing between the two edges is reduced incrementally until coincidence detector 120 again indicates the edges are coincident.
Assuming the edges are not sufficiently coincident for coincidence detector 120 to output a logic one (decision 335), the channel in tester 100 corresponding to pin 125A is adjusted to move the trailing edge on. pin 125A toward the leading edge on pin 125B (step 340). Coincidence detector 120 is then reset and the process returns to step 330 in which the new pair of edges, now more closely spaced, are presented on pins 125A and 125B.
By cycling through steps 330, 335, and 340, the delay separating the edges on A and B is again incrementally reduced until coincidence detector 120 indicates the two edges are coincident (in decision 335). The relative timing of the two edges (i.e., the second skew data) is then recorded in local memory within tester 100 (step 345).
In an illustrative example, the transition on pin 125B is held to a delay of 150 ps with respect to some reference as the transition on pin 125A is swept upward from 0 ps, in minimum increments equal to the tester resolution, for example 10 ps, from the same reference (larger increments can be used to approach coincidence). Coincidence detector 120 first indicates coincidence when the delay imposed on the edge on pin 125A is 240 ps from the reference. Next, the edge on pin 125B is held to a delay of 150 ps as the transition on pin 125A is swept downward from 1 ns. This time, coincidence detector 120 indicates coincidence when the delay imposed on the edge on pin 125A is 320 ps from the reference. From the exemplary data, one can assume the edges would be exactly coincident if tester 100 is set to provide the edge on pin 125A between 240 and 320 ps from the reference, or, subtracting the 150 ps delay associated with the edge on pin 125B, between 90 and 170 ps from the edge on pin 125B.
As a first approximation, the edges are deemed coincident at the midpoint (i.e., the average) of the 240 and 320 ps extremes, or at 280 ps from the reference. One can therefore conclude that imposing a delay of 130 ps (i.e., 280 psxe2x88x92150 ps) on pin 125A and zero delay on pin 125B will produce simultaneous transitions on pins 125A and 125B. The 130 ps average skew is then stored in memory in tester 100 (step 350).
To ensure the accuracy of skew data acquired using the above process, the measurements can be repeated in reverse order (i.e., beginning with the trailing edge on pin A), and/or sweeping the edge on pin B relative to pin A. The results of these tests can then be averaged.
Having discovered that the true skew between pins 125A and 125B is 130 ps, tester 100 can be set to delay edges on pin 125A by 130 ps relative to edges on pin 125B to provide coincident edges on respective pins 125A and 125B. And, once the skew is known for pins 125A and 125B in a particular test configuration, this knowledge can be used to precisely measure the performance of other circuits within DUT 110 that receive input signals on pins 125A and 125B.
Skew data similar to that obtained above for pins 125A and 125B is useful for each pin 125 on DUT 110. The method can be extended to obtain precise skew data for every pin relative to every other pin.
The method of FIGS. 1-3 works well, but does not take into account potential differences between the signal-propagation delays of the signal paths A and B from pins 125A and 125B to the respective input terminals of coincidence detector 120. Selecting similar paths can minimize these differences, but this is not always convenient and does not guarantee identical delays. There is therefore a need for a way to account for any differences between the signal propagation delays of paths leading to the coincidence detector.
The invention is directed to methods and circuits for accurately placing signal transitions, or xe2x80x9cedges,xe2x80x9d simultaneously on two or more pins of a programmable logic device (PLD). A test configuration in accordance with the invention measures the relative signal-propagation delays of a pair of signal paths A and B extending from respective PLD input pins to interior portions of the PLD. The difference between the signal-propagation delays is then stored for use in subsequent deskew operations.
In accordance with one embodiment of the invention, the signal-propagation delays of the signal paths are measured using a ring oscillator. The PLD is configured to instantiate the ring oscillator to selectively include either signal path in the ring. The oscillator exhibits a first oscillation period when the oscillator includes the first signal path, and exhibits a second oscillation period when the oscillator includes the second signal path. The difference between the first and second periods provides a measure of the difference between the signal propagation delays of the two paths of interest.
Having accounted for the delay difference between the two paths, the PLD is configured to include a coincidence detector having first and second input terminals each-connected to one of the signal paths. A conventional tester then applies substantially simultaneous signal transitions on each of the first and second PLD input pins. The tester adjusts the relative timing of the signal transitions until the coincidence detector indicates the transitions are coincident. The amount of offset necessary to provide coincident edges is then added to the difference between the signal-propagation delays associated with two paths. The resulting sum is stored in a database for later use in deskewing edges applied to the first and second PLD input pins.
The claims, and not this summary, define the scope of the invention.